Microchips (chips) are often designed using a hardware description language (HDL) specification of the circuitry and associated on-chip circuitry layout. Once specified, the HDL is synthesized into logic blocks that are placed on the chip, e.g., on a field programmable gate array (FPGA). On the chip, the various paths within the circuitry will have an associated delay with respect to signal propagation. The total delay of each path in the circuitry is defined by a logic delay portion and an interconnect delay portion. The design of logic elements within the circuitry affects the logic delay. The placement of logic elements on the chip affects the interconnect delay. Therefore, to adjust the delay of a given path in the circuit, as-defined on the chip, either the logic elements within the path need to be modified or the placement of the logic elements within the path with respect to each other needs to be modified.
When modifying a circuit to resolve timing failures due to excessive delay, the designer needs to be capable of identifying the paths causing the timing failures, and determine the most appropriate manner in which the paths should be modified to correct the associated timing failures. However, it is currently difficult, if not impossible, for a designer to consider a broad view of the circuit design when determining which paths should be modified and how the paths should be modified to resolve timing failures, i.e., whether the logic design of elements within the path should be modified or the placement of elements within the path should be modified.